Validation JIG-S1

Détails techniques

{
  "project": "F1SYH_TX1_S1_JIG",
  "status": "STRUCTURAL_PASS_RELEASE_REVIEW_REQUIRED",
  "checks": [
    {
      "check": "F1SYH_TX1_S1_JIG.kicad_pcb",
      "status": "PASS",
      "detail": "depth=0"
    },
    {
      "check": "F1SYH_TX1_S1_JIG.kicad_sch",
      "status": "PASS",
      "detail": "depth=0"
    },
    {
      "check": "BOM/PCB references",
      "status": "PASS",
      "detail": []
    }
  ],
  "warnings": [
    "ERC/DRC non exécutés.",
    "Mesures RF réelles requises.",
    "Schéma legacy à importer."
  ]
}